The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a bipolar integrated circuit.
Conventionally, an npn bipolar integrated circuit has been manufactured by the following method. An n.sup.+ -type buried layer 2 is selectively formed in a p-type silicon substrate 1. After an n-type silicon epitaxial layer 3 is formed to cover the p-type silicon substrate 1, a p.sup.+ -type isolation region 4 is selectively formed to isolate semiconductor elements from each other. The p.sup.+ -type isolation region 4 reaches the p-type silicon substrate 1. A p-type inner base region 5 and a p.sup.+ -type outer base region 6 are formed in the silicon epitaxial layer 3 (collector region) of an island shape isolated by the p.sup.+ -type isolation region 4. An n.sup.+ -type emitter region 7 and a collector electrode region 8 are formed in the p-type inner base region 5 and the n-type silicon epitaxial layer 3, respectively. Contact holes 10.sub.1 to 10.sub.3 are formed at parts of an insulating film 9 corresponding to the p.sup.+ -type outer base region 6, the n.sup.+ -type emitter region 7 and the n.sup.+ -type collector electrode region 8. An aluminum film is deposited on the entire surface of the insulating film 9. Thereafter, the aluminum is patterned to form base, emitter and collector electrodes 11 to 13. Thus, the npn bipolar integrated circuit is manufactured (FIG. 1). In the method for manufacturing the integrated circuit as described above, the p.sup.+ -type outer base region 6 and the n.sup.+ -type emitter region 7 are spaced apart by a predetermined length l in order to guarantee the breakdown voltage and to reduce the junction capacitance between the outer base and the emitter. However, when the p.sup.+ -type outer base region 6 is to be spaced apart from the n.sup.+ -type emitter region 7, the size becomes larger than the desired size by the length l. In other words, the length of the inner base region 5 becomes greater at the extra portion for mask alignment. Therefore, the resistance of the inner base increases, preventing high speed operation of the npn transistor and decreasing the integration density.
In addition to the bipolar integrated circut wherein the npn transistor is isolated from other circuit elements by the p.sup.+ -type isolation region 4 formed by isolation diffusion, a bipolar integrated circuit is also known wherein an npn transistor is isolated from other circuit elements by a thick buried oxide film. For example, FIG. 2 shows a transistor of a "walled-emitter" structure which has the n.sup.+ -type emitter region 7 formed in contact with an isolation oxide film 14. FIG. 2 is a sectional view showing the n.sup.+ -type emitter region 7 and the isolation oxide film 14 only in the uppermost location. Further, an emitter electrode is omitted. Referring to FIG. 2, reference numeral 5 denotes a p-type inner base layer; 3, an n-type epitaxial layer as a collector region; 2, an n.sup.+ -type buried layer; and 1, a p.sup.- -type silicon substrate. The same reference numerals in FIG. 2 denote the same parts as in FIG. 1. In a method for manufacturing the transistor shown in FIG. 2, the step of etching a relatively thick oxide film (not shown) on the n.sup.+ -type emitter region 7 is required prior to the formation of the n.sup.+ -type emitter region 7. In this step, the isolation oxide film 14 in the vicinity of the n.sup.+ -type emitter region 7 is deeply etched, so that a V-shaped groove 15 is formed. As a result, part of the n.sup.+ -type emitter region 7 in the vicinity of the isolation oxide film 14 is deeper than remaining area of the n.sup.+ -type emitter region 7. Therefore, the base width .DELTA.w as indicated by the broken line is narrowed, thus lowering the breakdown voltage (VCEO) of the transistor.